1. Field of the Invention
This invention relates in general to processor-based systems, and more particularly to a method, apparatus and program storage device for providing self-quiesced logic for handling an error recovery instruction such as a reset or self-test instruction.
2. Description of Related Art
A typical structure for a conventional computer system includes one or more processing units connected to a system memory device (random access memory or RAM) and to various peripheral, or input/output (I/O), devices such as a display monitor, a keyboard, a graphical pointer (mouse), and a permanent storage device (hard disk). The system memory device is used by a processing unit in carrying out program instructions, and stores those instructions as well as data values that are fed to or generated by the programs. A processing unit communicates with the other components by various means, including one or more interconnects (buses), or direct memory-access channels. A computer system may have many additional components, such as serial and parallel ports for connection to, e.g., printers, and network adapters. Other components might further be used in conjunction with the foregoing; for example, a display adapter might be used to control a video display monitor, a memory controller can be used to access the system memory, etc.
A bus architecture of a computer system conveys much of the information and signals involved in the computer system's operation. One or more busses are used to connect a central processing unit (CPU) to a memory and to input/output elements so that data and control signals can be readily transmitted between these different components. When the computer system executes its programming, it is imperative that data and information flow as fast as possible in order to make the computer as responsive as possible to the user. In typical hardware applications such as, graphics adapters, full motion video adapters, small computer systems interface (SCSI) host bus adapters, and the like, it is imperative that large block data transfers be accomplished expeditiously. These applications are just some examples of subsystems that benefit substantially from a fast bus transfer rate. In many computer system architectures of today, the majority of the above mentioned subsystems reside on the computer system's expansion bus.
The expansion bus is generally used as a method of adding functional components to the computer system. Devices are physically coupled to the expansion bus and use the expansion bus to communicate and exchange information. The peripheral component interconnect (PCI) bus comprises an industry standardized expansion bus architecture upon which many “peripheral” devices are manufactured.
In a typical computer system, a reset command may be issued or asserted by a component or device within the computer system. The reset command may instruct all of the components and devices within the computer system to reset to a state of initial conditions or an initial configuration. A component or device of a computer system receiving a reset command or in the process of executing a reset command may be said to be in reset or in a reset condition. A component or device of a computer system that is no longer receiving a reset command or has executed a reset command may be said to be out of reset.
In systems with a local processor, which handles error recovery, a reset of all the system, except the processor, is desirable in order to return the system to a known good state. Often the logic involved with the processor interface itself cannot be reset since it must actively participate in operations on the interface. It is clear that this logic is the most important to be at a known good state since it is involved in all accesses of the system by the local processor. Alternatively, the local processor may attempt to hold itself off the processor interface to the system for some defined amount of time until it believes the reset is completed. This can be especially difficult if the local processor instruction memory is accessed via the processor interface. These same difficulties are faced if the local processor wishes to instruct the system logic to perform a self-test.
In addition to the problems involved with resetting or testing logic on an active interface, the local processor must assure that any in progress data (e.g., posted write data to memory) has reached its destination prior to the procedure taking place or data may be lost. This can be difficult to determine and time consuming. It is desirable to limit the accesses to logic during error recovery as hang conditions may occur resulting in loss of error information and failure of error recovery.
It can be seen then that there is a need for a method, apparatus and program storage device for providing self-quiesced logic for handling an error recovery instruction such as a reset or self-test instruction.